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8.19.4.3 Asynchronous to Synchronous ODT Mode Transition during Power-Down Exit
If DLL is selected to be frozen in Precharge Power Down Mode by the setting of bit A12 in MR0 to ―0‖, there is also a transit ion period around power down
exit, where either synchronous or asynchronous response to a change in ODT must be expected from the DDR3 SDRAM.
This transition period starts t ANPD before CKE is first registered high, and ends t XPDLL after CKE is first registered high. t ANPD is equal to (WL - 1) and is
counted (backwards) from the clock cycle where CKE is first registered high.
ODT assertion during the transition period may result in an R TT change as early as the smaller of t AONPD min and (ODTLon*t CK(avg) + t AON min) and as late
as the larger of t AONPD max and (ODTLon*t CK(avg) + t AON max). ODT de-assertion during the transition period may result in an RTT change as early as the
smaller of t AOFPD min and (ODTLoff*t CK(avg) + t AOF min) and as late as the larger of t AOFPD max and (ODTLoff*t CK(avg) + t AOF max). See Table 13.
Note that, if AL has a large value, the range where R TT is uncertain becomes quite large. Figure 85 shows the three different cases: ODT_C,
asynchronous response before t ANPD ; ODT_B has a state change of ODT during the transition period; ODT_A shows a state change of ODT after the
transition period with synchronous response.
T0
T1
T2
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Tb0
Tb1
Tb2
Tc0
Tc1
Tc2
Td0
Td1
CK#
CK
CKE
Command
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Last sync, ODT
t ANPD
t AOFPD min
PD exit transition period
t XPDLL
RTT
RTT
ODTLoff + t AOF min
t AOFPD max
t AOFPD max
Sync or async, ODT
t AOFPD min
RTT
RTT
ODTLoff + t AOF max
ODTLoff
t AOF max
First async, ODT
t AOF min
RTT
RTT
TIME BREAK
TRANSITIONING
DON'T CARE
Figure 85 – Asynchronous to synchronous transition during Precharge Power Down
(with DLL frozen) exit (CL = 6; AL = CL - 1; CWL = 5; t ANPD = WL - 1 = 9)
Publication Release Date: Dec. 09, 2013
Revision A05
- 92 -
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